The invention relates to a method of manufacturing an integrated circuit for detecting infrared radiation comprising a semi-isolating substrate provided with a buried PIN photodiode, with a junction field effect transistor J-FET, whose gate is connected to the PIN photodiode and with a resistor R connected to the transistor, this method including the step of growing a first structure of epitaxial layers of semiconductor materials, in which the transistor of the J-FET type is formed, the step of growing a second structure of epitaxial layers of semiconductor materials, in which the PIN diode is formed, and the step of etching a pit in which the second structure of layers is formed.
The invention is used in the manufacture of infrared detectors, especially for use at the wavelengths 1.3 and 1.55 .mu.m in the field of telecommunication. The device according to the invention may be coupled, for example, to optical guides.
A manufacturing method for obtaining an integrated photodetector comprising a PIN photodiode, a field effect transistor of the J-FET type and a resistor is known from British Patent Application 2,168,528. According to this method, a pit is first formed by etching in a substrate of semi-isolating InP to receive the layers that will form the photodiode. These layers comprise a buffer layer of the n.sup.+ type, which also serves as n contact for the diode and is formed either by ion implantation or by LPE; and a buried epitaxial layer of GaInAs of the n.sup.- type formed by LPE, which fills the pit and flows out of the pit and extends flatly on the surrounding region. This method then comprises the step of etching this planar layer of GaInAs of the n.sup.- type until the upper part of the pit filled with this material surrounded by the substrate of InP is exposed; the epitaxial growth by LPE of GaInAs of the n-type or of GaInAsP of the n-type on the whole surface of the device to form the channel region of the J-FET; the epitaxial growth by LPE of GaInAs of the p-type or of InP of the p-type to form the gate of the J-FET; the local diffusion of zinc atoms to form the p-type region of the diode and the interconnection of the diode, the gate of the J-FET and the resistor to be formed. This method finally comprises etching steps to isolate the elements, except in the connection regions, and of depositing layers to form the resistor and the electrical contacts. Especially, the n contact of the diode is formed by exposing the layer of n.sup.+ -type InP during the manufacture of a MESA around the diode. The illumination of this diode is effected through the back surface of the substrate.
Now it appears that, in order to form during the same process a transistor of the J-FET type and a PIN diode, it is necessary to accurately control both the thicknesses of the layers required for forming these elements and the dopings of these layers because these thicknesses and these dopings are different for each of the structures of layers constituting these elements.
According to the known method, especially the p-type layer forming the p-type region of the diode can only have a very substantial thickness due to the chosen mode of use. Such a large thickness leads to a low quantum efficiency, which is detrimental to the performances of the diode.
Moreover, according to the known method, the diode can only be formed from a simple hetero-structure, which does not lead to optimal performances.
Besides, according to the known method, each of the layers is formed by LPE with a given growth doping and more particularly for obtaining the transistor, a layer of p-type GaInAs or of p-type InP is formed by LPE at the surface of a layer of n-type GaInAs or of n-type GaInAs.
Now it is always difficult to form two layers of opposite conductivity types at the surfaces one of the other by the same technology because the species serving to dope the first layer pollute the reactor and therefore the second layer during its formation. It is also difficult to form two layers of the same conductivity type doped at different levels by the same technology because the transition is then not abrupt and the layers are poorly differentiated. Therefore, care should be taken not to form the layer of the n.sup.+ -type and the layer of the n-type of the diode by the same technology, as is stated in the aforementioned document.
Otherwise, the known method includes a step by means of which an etching treatment is carried out to expose a surface comprising two zones of different materials: a first zone of n.sup.- -type GaInAs corresponding to the n-type region of the diode in the pit and a second zone surrounding the first zone and constituted by the material of the substrate of InP. Such an etching treatment can be effected only with great difficulty if a flat surface should be obtained because etching of different materials, such as GaInAs and InP, takes place with great different rates. Such a step must therefore absolutely be avoided.
It should further be noted that the known device can be illuminated only through the back surface of the substrate, which is a disadvantage in all the cases in which the photodetector device is not a discrete component, but is incorporated in an integrated circuit. In the latter case, a device must be provided which can be illuminated through the upper surface of the substrate.
The present invention proposes a method of manufacturing a photodetector device which permits of avoiding these different disadvantages and which can moreover be operated in a simple manner.